Zen bound 2 protrusion iv1/1/2023 ![]() ![]() ![]() ![]() This allows AMD to make the chiplets extremely compact. The reason the chiplet is so much smaller is that it doesn’t need memory controllers, it only has one IF link, and has no IO, because all of the platform requirements are on the IO die. AMD did not breakdown this 31.3 number into cores and 元, but one might imagine that the 元 might be approaching 50% of that number. Add two of these 60mm2 complexes with a memory controller, PCIe lanes, four IF links, and other IO, and a Zen+ zeppelin die was 213 mm2 in total.įor Zen 2, a single chiplet is 74mm2, of which 31.3 mm2 is a core complex with 16 MB of 元. With 12nm and the Zen+ core, AMD stated that a single core complex was ~60 square millimeters, which separates into 44mm2 for the cores and 16mm2 for the 8MB of 元 per CCX. AMD gave us some insight into how 7nm changed some of its designs, as well as the packaging challenges therein.Ī key metric given up by AMD relates to the core complex: four cores, the associated core structures, and then L2 and 元 caches. Even disregarding power and frequency, the ability to put structures into silicon and then integrate that silicon into the package, as well as providing power to the right parts of the silicon through the right connections becomes an exercise in itself. Moving down in node size brings up a number of challenges in the core and beyond. ![]()
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